Recently, requests for further miniaturization and high-integration of a semiconductor device have been increasing, and miniaturization of a MOS transistor according to a scaling law is already close to a limit. When miniaturization proceeds in such a manner, simple scaling of a gate length does not improve MOS device characteristics or circuit characteristics any more, and, on the contrary, rapidly brings about deterioration. However, when considering a reduction of a chip size or the like, it is essential to miniaturize a device size with generations.
In such circumstances, what is called a technology booster is getting introduced as a technology to further improve transistor characteristics at a scaling time of a gate length. Thereamong, a strained silicon technology can be cited as a technology being developed as the most promising technology. The strained silicon technology is a technology to improve transistor characteristics by applying a strain to a channel region of a MOS transistor by improving mobility of a carrier. As methods of a strain introduction to the channel region, there are developed a technique to embed materials having a lattice constant different from that of silicon into a source/drain region, a technique to control the strain by adjusting a formation condition of a gate insulation film as in Patent Document 1, and so on. Nowadays, the strain silicon technology has become essential as a characteristics improvement technology at a low cost, and it is important to improve the strain silicon technology for further improvement of characteristics of a CMOS transistor.
However, the former technique requires ion-implanting of different substances and different conditions for an n-type MOS transistor and for a p-type MOS transistor, while the latter technique requires forming with different film materials and a different number of layers for an n-channel MOS transistor and for a p-channel MOS transistor (hereinafter, referred to as n-type and p-type MOS transistors). In other words, in the above cases, there are problems that the number of processes increases, and furthermore, that a complicated and complex process is added. Further, even when control of the strain is tried with such an increase of the process number, it is difficult to effectively introduce strains appropriate for the n-type and p-type MOS transistors.
Thus, there is actively studied a technology to form an insulation film having a property of applying a tensile stress or a compressive stress to a channel region as a contact etching stop film (insulation film functioning as an etching stopper at a time of formation of a contact hole to a source/drain region in an interlayer insulation film) covering a gate electrode.
FIG. 33A and FIG. 33B are schematic cross-sectional views illustrating states that desired stresses are applied to channel regions. It should be noted that in FIG. 33A and FIG. 33B, source/drain regions are omitted for the sake of illustrative convenience.
As for an n-type MOS transistor, in order to improve its characteristics, a tensile stress is applied to a channel region, that is, a portion between source/drain regions of a semiconductor substrate to introduce a tensile strain. On the other hand, as for a p-type MOS transistor, in contrast, in order to improve its characteristics, it is necessary to apply a compressive stress to a channel region to introduce a compressive strain.
An n-type transistor is exemplified in FIG. 33A. In this n-type MOS transistor 100, a gate electrode 103 is pattern-formed on a silicon semiconductor substrate 101 via a gate insulation film 102, and a sidewall insulation film 104 is formed in a manner to cover only both side surfaces of the gate electrode 103. The sidewall insulation film 104 is formed, as necessary, to have a two-layer structure of an inside sidewall insulation film 104a and an outside sidewall insulation film 104b covering the inside sidewall insulation film 104a as illustrated.
In both sides of the gate electrode 103 are formed undepicted source/drain regions being a pair of n-type impurity diffusion regions made by introduction of a predetermined n-type impurity, while on an upper surface of the gate electrode 103 and upper surfaces of the source/drain regions are each formed silicide layers 105 for lower resistance. Further, a tensile stress film 106 which functions also as a contact etching stopper is formed on an entire surface in a manner to cover the gate electrode 103 and the sidewall insulation film 104. The tensile stress film 106 is an insulation film having a property of applying a tensile stress to the outside by contracting itself.
As described above, by forming the tensile stress film 106, stresses are applied in directions indicated by arrows in FIG. 33A and a tensile stress is applied to a channel region, so that a tensile strain is introduced.
On the other hand, as for a p-type MOS transistor 200, as illustrated in FIG. 33B, a gate electrode 203 is pattern-formed on a silicon semiconductor substrate 101 via a gate insulation film 202, and a sidewall insulation film 204 is formed in a manner to cover only both side surfaces of the gate electrode 203. The sidewall insulation film 204 is formed, as necessary, to have a two-layer structure of an inside sidewall insulation film 204a and an outside sidewall insulation film 204b covering the inside sidewall insulation film 204a as illustrated.
In both sides of the gate electrode 203 are formed undepicted source/drain regions being a pair of p-type impurity diffusion regions made by introduction of a predetermined p-type impurity, while on an upper surface of the gate electrode 203 and upper surfaces of the source/drain regions are each formed silicide layers 205 for lower resistance.
In the p-type MOS transistor 200, in order to improve characteristics, it is necessary to apply stresses in directions indicated by arrows in FIG. 33B and to apply a compressive stress to a channel region so that a compressive strain is introduced.    Patent Document 1: Japanese Laid-open Patent Publication No. 2003-45996
As described above, when introducing a strain into a channel region by using a contact etching stop film, it is necessary to apply stresses reverse to each other for an n-type MOS transistor and a p-type MOS transistor. Therefore, in a CMOS transistor being a complementary semiconductor device having an n-type MOS transistor and a p-type MOS transistor, in order to improve respective characteristics of the n-type MOS transistor and the p-type MOS transistor, it is necessary to form, as contact etching stop films, a tensile stress film for a p-type MOS transistor side and a compressive stress film for an n-type MOS transistor side, separately.
However, in a manufacturing process of the CMOS transistor, forming two kinds of contact etching stop films having properties different from each other as described above leads to an increase of the number of process steps and complication of the process. Thus, conventionally, more emphasis is placed on prevention of the increase of the number of process steps and complication of the process, and the CMOS transistor is created with either one of the n-type MOS transistor and the p-type MOS transistor being sacrificed. In such a case, if, for example, the tensile stress film is formed as the contact etching stop film in a manner to cover both the n-type MOS transistor and the p-type MOS transistor, the characteristics of the n-type MOS transistor can be improved, but deterioration of the characteristics of the p-type MOS transistor have to be accepted.
In one conductivity transistor, in spite of formation of an etching stop film which ordinarily has a property of giving a channel region a strain to improve characteristics of the other conductivity transistor and which gives the channel region a strain to deteriorate characteristics of that one conductivity transistor, in reality, a strain to improve characteristics of the transistor is given to the channel region and improvement of the characteristics of that one conductivity transistor is realized. An object of the present embodiments is, eventually in a complementary semiconductor device, in spite of formation of an etching stop film which ordinarily has a property of improving characteristics of one conductivity transistor and deteriorating characteristics of the other conductivity transistor in a manner to cover both n-channel transistor side and p-channel transistor side in order to prevent an increase of the number of process steps and complication of the process, to concurrently improve the characteristics of both the transistors and to realize a highly reliable semiconductor device and a manufacturing method thereof.